Title of Thesis: Fast Modular Exponentiation Using Residue Domain Representation: a Hardware Implementation and Analysis Title of Thesis: Fast Modular Exponentiation Using Residue Domain Repre- Sentation: a Hardware Implementation and Analysis

Title of Thesis: Fast Modular Exponentiation Using Residue Domain Representation: A Hardware Implementation and Analysis Christopher Dinh Nguyen, Master of Science, 2013 Thesis directed by: Alan T. Sherman, Associate Professor Department of Computer Science and Electrical Engineering Dhananjay S. Phatak, Associate Professor Department of Computer Science and Electrical Engineering Using modular exponentiation as an application, we engineered on FPGA fabric and analyzed the first implementation of two arithmetic algorithms in Reduced-Precision Residue Number Systems (RP-RNS): the partial-reconstruction algorithm and quotient-first scaling algorithm. Residue number systems (RNS) provide an alternative representation to the binary system for computation. They offer full parallel computation for addition, subtraction, and multiplication. However, base extension, division, and sign detection become harder operations. Phatak’s RP-RNS uses a time-memory trade-off to achieve O (lgN) running time for base extension and scaling, where N is the bit-length of the operands, compared with Kawamura’s Cox-Rower architecture and its derivatives, which appear to take O (N) steps and therefore O (N) delay to the best of our knowledge. We implemented the fully parallel RP-RNS architecture based on Phatak’s description and architecture diagrams. Our design decisions included distributing the lookup tables among each channel, removing the adder trees, and removing the parallel table access thus trading size for speed. In retrospect, we should have hosted the tables in memory off the FPGA. We measured the FPGA utilization, storage size, and cycle counts. The data we present, though less than optimal, confirms the theoretical trends calculated by Phatak. FPGA utilization grows proportional K logK where K is the number of hardware channels. Storage grows proportional to O (N lg lgN). When using Phatak’s recommendations, cycle count grows proportional to O (lgN). Our contributions include documentation of our design, architecture, and implementation; a detailed testing methodology; and performance data based on our implementation to enable others to replicate our implementation and findings. Fast Modular Exponentiation Using Residue Domain Representation: A Hardware Implementation and Analysis by Christopher Dinh Nguyen Thesis submitted to the Faculty of the Graduate School of the University of Maryland, Baltimore County in partial fulfillment of the requirements for the degree of Master of Science 2013